STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
The bit error rate for T1 ESF can be calculated from the one-second PMON
CRCE count by the following equation:
ꢁ
ꢀ
24
8000
24*193
.
.
/
/
ꢁ
log 1ꢂ
BEE
ꢀ
ꢀ
ꢀ
0 /
/
ꢀ
ꢀ
/
/
0
Bit Error Rate = 1 - 10
Figure 31: CRCE Count vs. BER (T1 ESF mode)
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-07
0
50
100
150
200
250
300
350
CRCE
For T1 SF format, the CRCE and FER counts are identical, but the FER counter
is smaller and should be ignored.
Figure 32: CRCE Count vs. BER (T1 SF mode)
20
18
16
14
Average Count Over
Many 1 Second Intervals
)
2
-
0
1
x
(
12
10
8
6
4
e
t
a
R
r
o
r
r
E
t
i
B
2
0
0
200
400
600
800
1000
1200
Bit Error Event Count Per Second
12.4 Using the Internal FDL Transmitter
It is important to note that access rate to the TDPR registers is limited by the rate
of the internal high-speed system clock which is either the DS3, DS1 or E1 clock.
Consecutive accesses to the TDPR Configuration, TDPR Interrupt Status/UDR
PROPRIETARY AND CONFIDENTIAL
140
PMC [ PMC-SIERRA, INC ]
