STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 28: FER Count vs. BER (E1 mode)
9
8
7
Average Count Over
Many 1 Second Intervals
6
5
4
3
2
1
0
0
50
100
150
200
250
Framing Bit Error Count Per Second
Since the maximum number of CRC sub-multiframes that can occur in one
second is 1000, the 10-bit FEBE and CRCE counters cannot saturate in one
second. Despite this, there is not a linear relationship between BER and CRC-4
-4
block errors due to the nature of the CRC-4 calculation. At BERs below 10 ,
there tends to be no more than one bit error per sub-multiframe, so the number
of CRC-4 errors is generally equal to the number of bit errors, which is directly
-4
related to the BER. However, at BERs above 10 , each CRC-4 error is often
due to more than one bit error. Thus, the relationship between BER and CRCE
-4
count becomes non-linear above a 10 BER. This must be taken into account
when using CRC-4 counts to determine the BER. Since FEBEs are indications of
CRCEs at the far end, and are accumulated identically to CRCEs, the same
explanation holds for the FEBE event counter.
The bit error rate for E1 can be calculated from the one-second PMON CRCE
count by the following equation:
ꢁ
ꢀ
8
8000
8*256
.
.
/
/
ꢁ
log 1ꢂ
CRCE
ꢀ
ꢀ
ꢀ
0 /
/
ꢀ
ꢀ
/
/
0
Bit Error Rate = 1 - 10
PROPRIETARY AND CONFIDENTIAL
138
PMC [ PMC-SIERRA, INC ]
