STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
12.2 Servicing Interrupts
The TECT3 will assert INTB to logic 0 when a condition which is configured to
produce an interrupt occurs. To find which condition caused this interrupt to
occur, the procedure outlined below should be followed:
1. Read the bits of the TECT3 Master Interrupt Source register (0020H) to
identify which of the eight interrupt registers (0021H-0028H) needs to be read
to identify the interrupt. For example, a logic one read in the DS3INT register
bit indicates that an interrupt identified in the Master Interrupt Source DS3
register produced the interrupt.
2. Read the bits of the second level Master Interrupt Source register to identify
the interrupt source.
3. Service the interrupt.
4. If the INTB pin is still logic 0, then there are still interrupts to be serviced.
Otherwise, all interrupts have been serviced. Wait for the next assertion of
INTB
12.3 Using the Performance Monitoring Features
The PMON blocks are provided for performance monitoring purposes. The DS3
PMON block is used to monitor DS3 performance primitives. The PMON blocks
within each T1/E1 Framer slice are used to monitor T1 or E1 performance
primitives. The counters in the DS3 PMON block has been sized as not to
saturate if polled every second. The T1/E1 PMON event counters are of
sufficient length so that the probability of counter saturation over a one second
interval is very small (less than 0.001%).
An accumulation interval is initiated by writing to one of the PMON event counter
register addresses or by writing to the Master Revision/Global PMON Update
register. After initiating an accumulation interval, 3.5 recovered clock periods
(RCLK for the DS3 PMON) must be allowed to elapse to permit the PMON
counter values to be properly transferred before the PMON registers may be
read.
The odds of any one of the T1/E1 counters saturating during a one second
sampling interval go up as the bit error rate (BER) increases. At some point, the
probability of counter saturation reaches 50%. This point varies, depending
upon the framing format and the type of event being counted. The BER at which
the probability of counter saturation reaches 50% is shown for various counters
in Table 6 for E1 mode, and in Table 7 for T1 mode.
PROPRIETARY AND CONFIDENTIAL
136
PMC [ PMC-SIERRA, INC ]
