PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name
Type
Pin
No.
Function
RAVS1[1]
RAVS1[2]
RAVS1[3]
RAVS1[4]
RAVS1[5]
RAVS1[6]
RAVS1[7]
RAVS1[8]
Analogue F22
Receive Analogue Ground (RAVS1[8:1]). RAVS1[8:1] supplies
ground for the receive LIU input equalizer. RAVS1[8:1] should be
connected to analogue GND.
Ground
J20
T22
U21
T1
P3
G2
D1
RAVS2[1]
RAVS2[2]
RAVS2[3]
RAVS2[4]
RAVS2[5]
RAVS2[6]
RAVS2[7]
RAVS2[8]
Analogue G20
Receive Analogue Ground (RAVS2[8:1]). RAVS2[8:1] supplies
ground for the receive LIU peak detect and slicer. RAVS2[8:1]
should be connected to analogue GND.
Ground
H20
T21
T19
T3
R1
F2
G4
QAVD[1]
QAVD[2]
QAVD[3]
QAVD[4]
Analogue F20
Quiet Analogue Power (QAVD[4:1]). QAVD[4:1] supplies power
Power
AA13 for the core analogue circuitry. QAVD[4:1] should be connected
T4
B10
to analogue +3.3 V.
QAVS[1]
QAVS[2]
QAVS[3]
QAVS[4]
Analogue V21
Quiet Analogue Ground (QAVS[4:1]). QAVS[4:1] supplies ground
for the core analogue circuitry. QAVS[4:1] should be connected
to analogue GND.
Ground
AA8
F4
B15
Digital Power and Ground Pins
VDD1V8[1]
VDD1V8[2]
VDD1V8[3]
VDD1V8[4]
Power
A16
B9
Core Power (VDD1V8[4:1]). The VDD1V8[4:1] pins should be
connected to a well decoupled +1.8V DC power supply.
W9
AA14
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
31
PMC [ PMC-SIERRA, INC ]
