PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
13
FUNCTIONAL TIMING
13.1 SBI BUS Interface Timing
Figure 26 – SBI BUS Functional Timing
REFCLK
C1FP
•••
•••
•••
•••
•••
•••
DATA[7:0]
C1
V3
V3
V3 DS0#4. V5 DS0#9.
PL
V5
DP
Figure 26 illustrates the operation of the SBI Bus, using a negative justification on the second to
last V3 octet as an example. The justification is indicated by asserting PL high during the V3
octet. The timing diagram also shows the location of one of the tributaries by asserting V5 high
during the V5 octet.
Note – the SBI ADD and DROP busses operate in an identical manner. Signal names on the
ADD bus have an A prepended to the names shown in Figure 26 (e.g, AC1FP, ADATA[7:0], etc.)
and those on the DROP bus have an D prepended to them (e.g, DC1FP, DDATA[7:0], etc.)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
210
PMC [ PMC-SIERRA, INC ]
