PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
13.2 Line Code Violation Insertion
Figure 27 – B8ZS Line Code Violation Insertion
B8ZS Signature Pattern
0
0 0 V B 0 V B
TCLK
continuous zeros
TDP
TXTIP
0 0 0 V
B
B 0 V
TXRING
B8ZS Signature Pattern
0
0 0 V B 0 V B
TCLK
TDP
continuous zeros
0 0 0 0
B
TXTIP
TXRING
B 0 V
LCVINS = 1 causes
omission of first bipolar
violation pulse.
The effect of setting the LCVINS bit of the Line Interface Diagnostics register is shown in Figure
27. TXTIP[X] and TXRING[X] have been shown as square NRZ pulses for illustrative purposes.
Setting LCVINS to a logic 1 generates one line code violation and 3 bit errors by causing the
omission of the first line code violation pulse when a string of 8 consecutive zeros occurs in the
unipolar data stream TDP. To generate another line code violation, the LCVINS bit must be reset
to logic 0 and then set to logic 1 again.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
211
PMC [ PMC-SIERRA, INC ]
