PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H: RLPS Configuration and Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
ALOSI
ALOSV
X
X
0
R/W
R/W
R/W
R
ALOSE
SQUELCHE
IDDQ_EN
DB_VALID
Unused
0
0
X
X
1
R/W
Reserved
Reserved:
The Reserved bit must be logic 1 for correct operation.
DB_VALID:
The DB_VALID bit indicates if the adaptive equalizer has stabilized. This bit is set if the
equalisation has not changed by more than 2dB (or +/-8 steps in the RAM table) in more than
a selectable count of sampling periods.
IDDQ_EN:
The IDDQ enable bit (IDDQ_EN) is used to configure the analogue receiver for IDDQ tests.
When IDDQ_EN is a logic 1, or the IDDQEN bit in the Master Test Control #1 register (004H)
is a logic 1, the digital outputs of the analogue receiver are pulled to ground.
SQUELCHE:
The output data squelch enable (SQUELCHE) allows control of data squelching in response
to an analogue loss of signal (ALOS) condition. When SQUELCHE is set to logic 1, the
recovered data are forced to all-zeros if the ALOSV register bit is asserted. When
SQUELCHE is set to logic 0, squelching is disabled.
ALOSE:
The loss of signal interrupt enable bit (ALOSE) enables the generation of device level
interrupt on a change of Loss of Signal status. When ALOSE is a logic 1, an interrupt is
generated by asserting INTB low when there is a change of the ALOSV status. When ALOSE
is set to logic 0, interrupts are disabled.
ALOSV:
The loss of signal value bit (ALOSV) indicates the loss of signal alarm state.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
152
PMC [ PMC-SIERRA, INC ]
