PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH:
XLPG Pulse Waveform Storage Data
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
WDAT[6]
WDAT[5]
WDAT[4]
WDAT[3]
WDAT[2]
WDAT[1]
WDAT[0]
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
WDAT[6:0]:
The WDAT[6:0] bits contain the write data to be stored in the pulse template RAM, as
addressed by the UI[2:0], SAMPLE[4:0] and WAVEFORM[3:0] bits in the Pulse Waveform
Storage Write Address registers. When writing to the RAM, the address must first be written
to the Pulse Waveform Storage Write Address registers. Writing to the Pulse Waveform
Storage Data register triggers the transfer of data. If the UI portion of the address is 0, 1, 2 or
3, WDAT[6:0] are transferred to internal holding registers. If the UI portion of the address is 4,
WDAT[6:0] are combined with the contents of the holding registers to form a 35-bit long word
which is then stored in the pulse template RAM. Waveform samples must therefore be
written in groups of 5 and within each group of 5 writes, the waveform number and sample
selector must remain constant and the unit interval selector must be set to 0x0, 0x1, 0x2, 0x3
and 0x4 in sequence.
WDAT[6:0] are coded in signed magnitude representation. WDAT[6] is the sign bit, WDAT[5]
is the most significant data bit and WDAT[0] is the least significant data bit. The data values
thus can range from –63 to +63.
See the Operation section for more details on setting up custom waveform templates.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
151
PMC [ PMC-SIERRA, INC ]
