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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
Register 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H: XLPG Control/Status  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
R/W  
HIGHZ  
ARST  
1
0
X
0
X
0
0
1
Unused  
R/W  
R
INITRAM  
OVRFLW  
Reserved  
Reserved  
Reserved  
R/W  
R/W  
R/W  
HIGHZ:  
The HIGHZ bit controls tristating of the TXTIP[x] and TXRING[x] outputs. When the HIGHZ  
bit is set to a logic 0, the outputs are enabled. When the HIGHZ bit is set to a logic 1, the  
outputs are put into high impedance. Setting HIGHZ to logic 1 has the same effect as setting  
SCALE[4:0] to 00H.  
ARST:  
The Analogue Reset bit (ARST) resets the analogue portion of the XLPG (without affecting  
the digital portion) when set to logic 1.  
INITRAM:  
The Waveform Storage RAM initialisation bit (INITRAM) causes the XPLG waveform storage  
RAM to be initialised to 12 standard waveform patterns when set to logic 1. This bit remains  
at logic 1 while the initialisation is in progress and is cleared to logic 0 when the initialisation  
has completed.  
The 12 waveform patterns to which the RAM is initialised are listed in Table 20 thru Table 29,  
Table 37 and Table 38.  
OVRFLW:  
The overflow detection value bit (OVRFLW) indicates the presence or absence of an overflow  
condition in the waveform computation pipeline. An overflow occurs when the sum of the five  
unit interval (UI) samples exceeds the maximum D/A value. The XLPG detects overflows and  
saturates the output value to minimize their impact on the output signal. Overflows can easily  
be eliminated by changing the waveform programming. This status bit is set to logic 1 when  
an overflow condition is detected and it is reset to logic 0 only when this register is read. It is  
suggested that this register be read twice after the programming of a new waveform and  
transmission of data to ensure the maximum output amplitude is never exceeded.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
146  
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