PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H: PRBS Error Count #3
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
ERRCNT[23]
ERRCNT[22]
ERRCNT[21]
ERRCNT[20]
ERRCNT[19]
ERRCNT[18]
ERRCNT[17]
ERRCNT[16]
X
X
X
X
X
X
X
X
ERRCNT[23:0]:
ERRCNT[23:0] contain the error counter holding register. The value in this register
represents the number of bit errors that have been accumulated since the last accumulation
interval, up to a maximum (saturation) value of 224-1. Note that bit errors are not accumulated
while the pattern detector is out of sync.
The Error Count registers for each individual PRBS generator/checker are updated by writing
to any one of the Error count registers. Alternatively, the Error Count registers are updated
with all other octant counter registers by writing to the Line Interface Interrupt Source #1 /
PMON Update register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
145
PMC [ PMC-SIERRA, INC ]
