PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H: IBCD Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Reserved
Unused
Unused
Unused
DSEL1
DSEL0
ASEL1
ASEL0
0
X
X
X
0
0
0
0
R/W
R/W
R/W
R/W
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register provides the selection of the Activate and De-activate loopback code lengths (from 3
bits to 8 bits) as follows:
Table 12 – Loopback Code Configurations
DEACTIVATE Code
ACTIVATE Code
DSEL1
DSEL0
ASEL1
ASEL0
CODE LENGTH
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
5 bits
6 (or 3*) bits
7 bits
8 (or 4*) bits
Note:
3-bit and 4-bit code sequences can be accommodated by configuring the IBCD for 6 or 8 bits and
by programming two repetitions of the code sequence.
The Reserved bit is used for production test purposes only. The Reserved bit must be logic 0 for
normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
126
PMC [ PMC-SIERRA, INC ]
