PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH: TJAT Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
CENT
X
X
X
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
UNDE
OVRE
FIFORST
LIMIT
CENT:
The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least
4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is
enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods
following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this
384 UI period, the period will be extended by the number of UI that the EMPTY or FULL
alarm persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set
to logic 0, the self-centering function is disabled, allowing the data to pass through
uncorrupted during EMPTY or FULL alarm conditions.
The recommended value of CENT is logic 1.
UNDE:
Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low.
OVRE:
Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low.
FIFORST:
Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by software. When
FIFORST is logic 1, writing to the PLL Divider Control Registers N1 and N2 will cause both
the PLL and FIFO to reset. When FIFORST is logic 0, writing to the Divider Control Registers
N1 and N2 will cause only the PLL to reset.
LIMIT:
Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to
increase or decrease the frequency of the smooth output clock whenever the FIFO is within
one UI of overflowing or underflowing. This limiting of jitter ensures that no data is lost during
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
124
PMC [ PMC-SIERRA, INC ]
