PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH: TJAT Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
OVRI
X
X
X
X
X
X
X
X
R
R
UNDI
UNDI:
The UNDI bit is asserted when an attempt is made to read data from the transmit FIFO when
the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred.
Reading this register will clear the UNDI bit to logic 0.
OVRI:
The OVRI bit is asserted when an attempt is made to write data into the transmit FIFO when
the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading
this register will clear the OVRI bit to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
121
PMC [ PMC-SIERRA, INC ]
