PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 395H: EXSBI Master Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Reserved
Unused
0
X
0
0
0
0
X
0
R
R
R
R
DCRI_SHDW
PERRI_SHDW
FIFO_UDRI_SHDW
FIFO_OVRI_SHDW
Unused
R
C1FP_SYNCI
C1FP_SYNCI:
This bit is set when a AC1FP realignment has been detected. Reading this register clears this
interrupt source.
FIFO_OVRI_SHDW:
This bit is a shadow of the FIFO_OVRI bit in the EXSBI FIFO Overrun Interrupt Status
Register. It is set when the FIFO_OVRI bit is set and the interrupt enable FIFO_OVRE is set.
Reading this register has no affect on this interrupt source.
FIFO_UDRI_SHDW:
This bit is a shadow of the FIFO_UDRI bit in the EXSBI FIFO Underrun Interrupt Status
Register. It is set when the FIFO_UDRI bit is set and the interrupt enable FIFO_UDRE is set.
Reading this register has no affect on this interrupt source.
PERRI_SHDW:
This bit is a shadow of the PERRI bit in the EXSBI Parity Error Interrupt Reason Register. It
is set when the PERRI bit is set and the interrupt enable SBI_PERR_EN is set. Reading this
register has no affect on this interrupt source.
DCRI_SHDW:
This bit is a shadow of the DCRI bit in the EXSBI Depth Check Interrupt Status Register. It is
set when the DCRI bit is set and the interrupt enable DCR_INT_EN is set. Reading this
register has no affect on this interrupt source.
Reserved:
The reserved bit must be set to 0 for correct operation of the OCTLIU device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
100
PMC [ PMC-SIERRA, INC ]
