PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
RRISE:
The RRISE bit configures the interface to update the multifunction outputs
RDD/RDP[X] and RLCV/RDN[X] on the rising edge of RCLKO[X]. When
RRISE is set to logic 1, the interface is enabled to update the RDD[X]/TDP[X]
and RLCV/RDN[X] output pins on the rising RCLKO[X] edge. When RRISE is
set to logic 0, the interface is enabled to update the outputs on the falling
RCLKO[X] edge.
AUTO_LLB_EN:
When the AUTO_LLB_EN bit is set to logic 1 and the IBCD is enabled in the
receive path, then when the IBCD in a quadrant detects the inband loopback
activate code, the quadrant is immediately placed in line loopback mode. The
quadrant is taken out of line loopback when the inband loopback deactivate
code is detected, or when AUTO_LLB_EN is written with a logic zero.
Whenever the quadrant is placed in line loopback mode due to the reception
of an inband loopback code, the AUTO_LLB bit will be set to logic 1 in the
Diagnostics register. AUTO_LLB_EN should not be set to logic 1 if the DJAT
is bypassed (FIFOBYP=1), or if DJATTX =0. AUTO_LLB_EN has no effect
when IBCDTX =1.
AUTO_AIS_EN:
When set to logic 1, the AUTO_AIS_EN bit enables the insertion of AIS in the
receive path whenever the quadrant is in line loopback mode due to the
reception of an inband line loopback activate code. AUTO_AIS_EN has no
effect when AUTO_LLB_EN is a logic zero.
BPVCNT:
The BPVCNT bit enables only bipolar violations to indicate line code
violations and be accumulated in the LCV_PMON LCV Count registers.
When BPVCNT is set to logic 1, only BPVs not part of a valid AMI, B8ZS, or
HDB3 signature (depending on the configuration of the receiver) generate an
LCV indication and increment the LCV_PMON LCV counter. When BPVCNT
is set to logic 0, both BPVs not part of a valid signature and excessive zeros
generate an LCV indication and increment the LCV_PMON LCV counter.
Excessive zeros is defined for this operation to be a sequence of zeros
greater than 15 bits long for an AMI coded T1 signal, greater than 7 bits long
for a B8ZS coded signal, and greater than 3 bits long for an E1 signal.
CEPT:
The CEPT bit configures the receiver for E1 applications. When CEPT is set
to logic 1, the receiver is configured for E1 applications. When CEPT is set to
logic 0, the receiver is configured for T1 applications. All CEPT bits in all four
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
56
PMC [ PMC-SIERRA, INC ]
