PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Register 000H, 040H, 080H, and 0C0H: Receive Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RDPINV
RDNINV
0
0
0
0
0
0
0
0
RDUAL
RRISE
AUTO_LLB_EN
AUTO_AIS_EN
BPVCNT
CEPT
These registers enable the Receive Interface to handle the various input and
output waveform formats.
RDPINV,RDNINV:
The RDPINV and RDNINV bits enable the Receive Interface to logically invert
the signals output on multifunction pins RDD/RDP[X] and RLCV/RDN[X],
respectively. When RDPINV is set to logic 1, the interface inverts the output
on RDD/RDP[X]. When RDPINV is set to logic 0, the interface outputs
RDD/RDP[X] normally. When RDNINV is set to logic 1, the interface inverts
the output on RLCV/RDN[X]. When RDNINV is set to logic 0, the interface
outputs RLCV/RDN[X] normally.
RDUAL:
RDUAL configures the RDD/RDP[X] and RLCV/RDN[X] outputs to unipolar or
bipolar form. When the RDUAL bit is set to logic 1, the bipolar outputs
RDP[X] and RDN[X] are enabled. When the RDUAL bit is set to logic 0, the
unipolar outputs RDD[X] and RLCV[X] are enabled. The RDUAL bit is
logically "ORed" with the RDUAL input pin. If either are set to logic 1, then
the bipolar outputs RDP and RDN will be enabled. If the XIBC or PRSG are
in the receive path, they will be bypassed if RDUAL is set. Also, though
bipolar violations in the input data will appear on RDP and RDN, the IBCD
and PRSM blocks will operate on a HDB3/B8ZS/AMI decoded version of the
data, depending on the configuration of CDRC. Note that the DCR bit in the
CDRC Configuration register (010H, 050H, 090H, and 0D0H) takes
precedence over the RDUAL bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
55
PMC [ PMC-SIERRA, INC ]
