PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
9.14 Register Memory Map
Address
Register
#1
# 2
# 3
# 4
000H
001H
002H
003H
004H
005H
040H
041H
042H
043H
044H
045H
080H
081H
082H
083H
084H
085H
0C0H Receive Configuration
0C1H Transmit Configuration
0C2H TX/RX Block Placement
0C3H Interrupt Source
0C4H Reserved
0C5H Diagnostics
006H
Master Test
007H
Revision/Chip ID/Global Monitoring
Update
008H
009H
Interrupt Quadrant ID
TOPS Master Clock
Configuration/Clock Activity Monitor
046H
086H
087H
088H
089H
08AH
08BH
0C6H Reserved
047H
048H
049H
04AH
04BH
0C7H Reserved
0C8H Reserved
0C9H Reserved
00AH
00BH
0CAH TOPS Clock Timing Options
0CBH LCODE Transmit Line Code
Configuration
00CH
00DH
00EH
00FH
010H
011H
04CH
04DH
04EH
04FH
050H
051H
08CH
08DH
08EH
08FH
090H
091H
0CCH Reserved
0CDH Reserved
0CEH Reserved
0CFH Reserved
0D0H CDRC Configuration
0D1H CDRC Interrupt Enable
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
51
PMC [ PMC-SIERRA, INC ]
