PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
4. All QDSX digital outputs and bidirectionals have 2 mA drive capability. The
data bus outputs, D[7:0], and CLKO8X have 4 mA drive capability. For board
layouts, care should be maken with the 2mA drive RCLKO[4:1] signals to
guarantee clock signal integrity.
5. The recommended power supply sequencing is as follows:
5.1VDDI[3:1] power must be supplied either before VDDO[6:1] or
simultaneously with VDDO[6:1]. Connection of VDDI[3:1] and VDDO[6:1] to a
common VDD power plane is recommended.
5.2The VDDI[3:1] and VDDO[6:1] power must be applied before input pins
are driven or the input current per pin must be limited to less than 20 mA.
5.3Analog power supplies must be applied after both VDDI[3:1] and
VDDO[6:1] have been applied or the they must be current limited to the
maximum latchup current specification. (100 mA). In operation the differential
voltage measured between TAVD[4:1] and RAVD[4:1] supplies and VDDI[3:1]
and VDDO[6:1] must be less than 0.5 volt.The relative power sequencing of
TAVD[4:1] and RAVD[4:1] power supplies is not important.
5.4Power down the device in the reverse sequence.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
