PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Internal high speed timing for all quadrants of the QDSX is provided by a
common 37.056 MHz or 49.152 MHz master clock. This master clock rate is
required for applications where QDSX provides jitter attenuation. For
applications where QDSX is not required to attenuate jitter, a 12.352 MHz or
16.384 MHz clock may be used as the master clock and used directly as the
internal 8X high speed clock.
Diagnostic loopback is provided and the loopback may be invoked past the
analog transmit outputs using the driver performance monitors or invoked prior to
the conversion to analog. Line loopback with jitter attenuation is provided and
may be enabled for automatic operation based on detected inband loopback
codes.
The QDSX detects framed or unframed inband loopback code sequences from
the received input pulses. Any arbitrary code from three to eight bits in length
can be declared to be the activate and deactivate codes by writing to
configuration registers. The inband loopback code detector can optionally be
moved to the transmit side where it detects inband loopback codes in the
unipolar input transmit data stream. For framed inband loopback code
sequences, it is expected that the framing bit overwrites the inband loopback
code bit.
The QDSX may insert unframed inband loopback code sequences into the
transmitted PCM data stream. These codes consist of continuous repetitions of
specific bit sequences. Any arbitrary code from three to eight bits in length is
programmable by writing to configuration registers. This unframed inband
loopback code insertion may optionally be switched to the receive side where it
overwrites the data from the slicer.
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The QDSX may insert an unframed 2 -1 O.151 compatible pseudo-random bit
sequence into the transmitted PCM data stream. Optionally, the PRBS insertion
may be switched to the receive side where it overwrites the data from the slicer.
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The QDSX detects an unframed 2 -1 O.151 compatible pseudo-random bit
sequence input to the receive slicer. This PRBS detector can operate in the
-2
presence of a 10 bit error rate. Bit errors are detected and recorded. The
PRBS detector can optionally be switched to the transmit side where it can
detect unframed PRBS data from the unipolar input transmit data stream.
The QDSX operates in conjunction with external line coupling transformers,
resistors, and capacitors. An external crystal may be used for high speed timing
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
