PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Figure 5
- Loopback Modes
PR SM
PR BS
DETECTOR AND
ERROR COUN TER
IBC D
IN-BAN D LOOP-
BACK C ODE
DETECTOR
TR AN SM IT TE R
TDD/TDP[4:1]
PRS G
PRB S
GENERA TOR
XIB C
IN-BAN D LOOP-
BACK C ODE
GENERATO R
LC OD E
AM I/B 8ZS/H DB3
LIN E
XP LS
ANA LOG
PULS E
TXTIP[4:1 ]
D JAT
DIGI TAL JIT TER
ATTENUATOR
TDN[4:1]
ENCODER
GENERA TOR
TCLKI[4:1]
TXRING[4:1 ]
TC[4:1]
TO PS
XCLK/VCLK
TIM ING OPTIONS
LINE LB
D MLB
D IA LB
CLKO8X/CLKO1X
RE CE IV ER
CD R C
CLOCK AND
DATA
R SLC
ANA LOG
PULS E
SLICER
RXTIP[4:1]
RXRING[4:1]
RC[4:1]
XIB C
IN-BAND LOOP -
BACK CODE
PR SG
PR BS
GENERATOR
RDD/RDP/SDP[4:1]
RLCV/RDN/SDN[4:1]
D JAT
DIGITA L JITTE R
ATTEN UATOR
RECOVERY
GENERA TOR
RCLKO[4:1]
IBC D
LC V_PM ON
LINE CODE
VIO LATI ON
COUNTER
IN-BAND LOOP -
BACK CODE
DETECTOR
PR SM
PRBS
DETECTOR AND
ERROR COUN TER
C ON T R OL S IG N AL S
B O UN DAR Y SC AN
IEEE P1149.1
JTAG Tes t
Microproces sor Interface or
Hardware Control Signals
Access Port
Note:
Dashed boxes show optional placement of blocks. Default placement of the
block is shown in solid boxes.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
PMC [ PMC-SIERRA, INC ]
