PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
5
BLOCK DIAGRAM
Figure 4
- Normal Operating Mode
PR SM
P RBS
DETECTOR AND
IBC D
IN- BAND LOOP-
BACK C ODE
DETECTOR
TR ANSMITTER
ERR OR COUNTER
TDD/TDP[4:1]
PR S G
PR BS
GENERA TOR
XIB C
IN- BAND LOOP-
BACK C ODE
GENERA TOR
LC OD E
AM I/B8Z S/HDB3
LINE
XP LS
ANA LOG
P ULS E
TXTIP [4:1 ]
D JAT
DIGITAL JITTER
ATTENUATOR
TDN[4:1]
TCLKI[4:1]
ENC ODER
GEN ERA TOR
TXR ING[4 :1]
TC[4:1 ]
TOPS
XCLK/VCL K
TIM ING OPTI ONS
CLKO8X/C LKO1X
REC EIVER
C D RC
CLO CK AND
DATA
R SLC
A NALO G
PUL SE
RXTIP [4:1]
RXRING[4:1]
RC[4:1]
XIB C
IN- BAND LOOP-
BACK C ODE
PR S G
PRBS
GEN ERA TOR
RDD/RDP/SDP[4:1]
RLCV/RDN/SDN[4:1]
D JAT
DIGITAL JITTER
ATTENUATOR
RE COVERY
SLICER
GEN ERATO R
RCLKO[4:1]
IBC D
LC V_PM ON
IN- BAND LOOP-
BACK C ODE
DETECTOR
LINE C ODE
VI OLAT ION
COUN TER
PR SM
PR BS
DETECTOR A ND
ERR OR COUNTER
C ON TROL SIGN ALS
B OU N D AR Y SC AN
IEEE P1149.1
JTAG Te s t
Acces s Port
Microproces s or Interface or
Hardware Control Signals
Note:
Dashed boxes show optional placement of blocks. Default placement of the
block is shown in solid boxes.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
13
PMC [ PMC-SIERRA, INC ]
