PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
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DESCRIPTION
The PM4314 QDSX Quad T1/E1 Line Interface Device is a monolithic integrated
circuit that supports DSX-1 and CEPT E1 compatible transmit and receive
interfaces for four 1.544 Mbit/s or 2.048 Mbit/s data streams.
In the incoming direction, the DSX-1/E1 signals for each quadrant of the QDSX
are first processed by a receive data slicer. The receive data slicer converts the
line signal received via a coupling transformer to dual rail RZ digital pulses.
Adaptation for attenuation is achieved using an integral peak detector that sets
the slicing levels. Through use of passive external attenuation circuitry, either
terminated or bridge monitored DSX-1/E1 signal levels can be accommodated.
The low signal level condition or signal squelch may be enabled to generate
interrupts. Clock and data are recovered from the dual rail RZ digital pulses
using a digital phase-locked loop that provides excellent high frequency jitter
accommodation. The recovered data is decoded using B8ZS, HDB3, or AMI line
code rules and is presented either as a DS-1/E1 stream or presented in an
undecoded dual rail NRZ format. Loss of signal and line code violations are
detected as well as 8 successive zeros/4 successive zeros, and the B8ZS/HDB3
signature. The presence of programmable inband loopback codes is also
detected. These various events or changes in status may be enabled to
generate interrupts. Additionally, line code violations are indicated on outputs.
In the outgoing direction, each quadrant of the QDSX may accept either a DS-
1/E1 stream to be encoded using B8ZS, HDB3, or AMI line code rules, or it may
accept pre-encoded data in dual rail NRZ format. Jitter attenuation is provided
by passing outgoing data through a FIFO. A low jitter clock is generated by an
integral digital phase-locked loop and is used to read data from the FIFO. FIFO
overrun or underrun may be enabled to generate interrupts. Alarm indication
signal (all ones) may be substituted for the FIFO data. The digital data is
converted to high drive, dual rail RZ pulses that drive the DSX-1/E1 interface
through a coupling transformer. The shape of the pulses is user programmable
to ensure that the DSX-1/E1 pulse template is met after the signal is passed
through different cable lengths or types. Driver performance monitoring is
provided and may be enabled to generate interrupts upon driver failure.
The jitter attenuation function can optionally be moved to the receive side. The
recovered clock and data is passed through the jitter attenuator before being
presented at the digital receive outputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
