PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Register 029H, 069H, 0A9H, 0E9H: PRSM Control/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R
PRBSINV
Reserved
OOSE
OOSI
0
0
0
X
X
0
R
OOS
R/W
R
INTE
INT
X
X
R
OVR
This register shows the PRBS monitor synchronization state and enables an
interrupt to be generated whenever synchronization is lost or regained. This
register also enables an interrupt to be generated whenever the PRBS error
counter data is transferred into the PRSM holding registers. The configuration
register also contains status information as to whether these holding registers
have been overrun.
PRBSINV:
When the PRBSINV bit is set, the PRSM inverts the incoming data. This will
allow it to synchronize to an inverted pseudorandom bit sequence. In the
default setting, the PRSM synchronizes to a non-inverted sequence. An
15
inverted 2 -1 PRBS will contain at most 15 consecutive zeroes, while a non-
15
inverted 2 -1 PRBS will contain at most 14 consecutive zeroes. Some
testers may only support the inverted sequence.
Reserved:
The Reserved bit must be programmed to logic 0 for proper operation.
OOSE:
The OOSE bit controls the generation of a microprocessor interrupt when a
change of PRBS synchronization state occurs A logic 1 bit in the OOSE
position enables the generation of an interrupt; a logic 0 bit in the OOSE
position disables the generation of an interrupt. The interrupt is cleared by
reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
96
PMC [ PMC-SIERRA, INC ]
