PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Registers 024H, 064H, 0A4H and 0E4H: XIBC Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
EN
Reserved
Unused
Unused
Unused
Unused
CL1
0
0
X
X
X
X
0
R/W
R/W
CL0
0
These registers control the transmission of T1 inband loopback activate and
deactivate codes.
EN:
The EN bit controls whether the inband code is transmitted or not. A logic 1
in the EN bit position enables transmission of inband codes; a logic 0 in the
EN bit position disables inband code transmission.
Reserved:
This bit is reserved and should be set to logic 0 for proper operation.
CL1, CL0:
The bit positions CL[1:0] (bits 1 & 0) of this register indicate the length of the
inband loopback code sequence, as follows:
CL1
CL0
Code Length
0
0
1
1
0
1
0
1
5
6
7
8
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
92
PMC [ PMC-SIERRA, INC ]
