PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Register 027H, 067H, 0A7H, 0E7H: PRSG Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
X
X
X
X
X
0
Unused
Unused
Unused
R/W
R/W
R/W
PRBSINV
PRBSERR
PRBSGEN
0
0
This register enables the PRSG pseudo-random bit sequence generation.
PRBSINV:
15
When the PRBSINV bit is set, the PRSG block inverts the 2 -1 PRBS data
15
before transmission. An inverted 2 -1 PRBS will contain at most 15
15
consecutive zeroes, while a non-inverted 2 -1 PRBS will contain at most 14
consecutive zeroes. Some testers may only support the inverted sequence.
PRBSGEN:
15
The PRBSGEN bit enables the PRSG block to insert the 2 -1 PRBS data
stream into the transmit data stream. When PRBSGEN is set to logic 1, the
PRSG block will overwrite the data stream with the PRBS data stream. When
PRBSGEN is set to logic 0, the PRBS generation is disabled.
PRBSERR:
When the PRBSERR bit is written with a logic 1, a single error is inserted in
the pseudo-random bit stream by inverting a single bit. To insert another bit
error, the PRBSERR bit must be written with a logic 0, and then re-written
with another logic 1. At least one bit period should elapse between writing
PRBSERR 0 and writing it 1 again, or vice versa, if an error is to be
successfully inserted. PRBSERR has no effect when PRBSGEN is set to 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
95
PMC [ PMC-SIERRA, INC ]
