PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Register 02BH, 06BH, 0ABH, 0EBH: PRSM Bit Error Event Count MSB
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
BER[15]
BER[14]
BER[13]
BER[12]
BER[11]
BER[10]
BER[9]
X
X
X
X
X
X
X
X
BER[8]
These holding registers indicate the number of bit error events that occurred
during the previous accumulation interval. The contents of these registers are
valid 2 µs after a transfer is triggered by a write to any one of the PMON’s
holding register addresses, or to register 007H.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
100
PMC [ PMC-SIERRA, INC ]
