Signal Ball Description
PLX Technology, Inc.
3.2
Abbreviations
The following abbreviations are used in the signal tables provided in this chapter.
Table 3-1. Ball Assignment Abbreviations
Abbreviation
Description
#
Active-Low signal
1.15V 3ꢀ (PEX 8532AA) Power (VDD10A) balls for SerDes Analog circuits
APWR
1.0V 5ꢀ (PEX 8532BA/BB/BC) Power (VDD10A) balls for SerDes Analog circuits
Differential low-voltage, high-speed, CML negative Clock inputs
Differential low-voltage, high-speed, CML positive Clock inputs
Differential low-voltage, high-speed, CML negative Receiver inputs
Differential low-voltage, high-speed, CML positive Receiver inputs
Differential low-voltage, high-speed, CML negative Transmitter outputs
Differential low-voltage, high-speed, CML positive Transmitter outputs
1.15V 3ꢀ (PEX 8532AA) Power (VDD10) balls for low-voltage Core circuits
1.0V 5ꢀ (PEX 8532BA/BB/BC) Power (VDD10) balls for low-voltage Core circuits
Common Ground (VSS) for all circuits; also associated with VSS_THERMAL (thermal ground)
Input (signals with weak internal pull-up resistors)
CMLCLKna
CMLCLKpa
CMLRn
CMLRp
CMLTn
CMLTp
CPWR
GND
I
I/O
Bi-Directional programmable signal (input or output)
I/OPWR
O
3.3V Power (VDD33) balls for Input and Output interfaces
Output
PLL_GND
PLLPWR
PU
PLL Ground connection
3.3V Power (VDD33A) balls for PLL circuits
Pull-up resistor (recommended value between 3K to 10K Ohms)
Differential low-voltage, high-speed, I/O signal pairs (negative and positive)
1.15V 3ꢀ (PEX 8532AA) Power (VDD10S) balls for SerDes Digital circuits
1.0V 5ꢀ (PEX 8532BA/BB/BC) Power (VDD10S) balls for SerDes Digital circuits
Strapping balls cannot be left floating on the board
SerDes
SPWR
STRAP
a. For REFCLK input, CML source is recommended; however, LVDS source is supported.
16
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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