PEX 8532 Applications
PLX Technology, Inc.
2.3
Software Usage Model
From a system model viewpoint, each PCI Express port is a virtual PCI-to-PCI bridge device, with its
own set of PCI Express Configuration registers. The BIOS or Host can configure the other ports by way
of the upstream port, using Conventional PCI enumeration. The virtual PCI-to-PCI bridges within the
PEX 8532 are compliant to the PCI and PCI Express system models. The Configuration Space registers
(CSRs) in a virtual primary/secondary PCI-to-PCI bridge are accessible by Type 0 Configuration
requests through the virtual primary bus interface (matching Bus, Device, and Function Numbers).
2.3.1
2.3.2
System Configuration
The virtual PCI-to-PCI bridges within the PEX 8532 are compliant with the PCI and PCI Express
system models. The Configuration Space Registers (CSRs) in a virtual primary/secondary PCI-to-PCI
bridge are accessible by Type 0/1 Configuration requests, by way of the virtual primary bus interface
(matching Bus, Device, and Function Numbers).
Interrupt Sources and Events
The PEX 8532 supports the INTx Interrupt message type (compatible with PCI r2.3 Interrupt signals) or
Message Signaled Interrupts (MSI), when enabled. The PEX 8532 generates messages for PCI Express
Baseline and Advanced Error Reporting error reporting mechanisms. The PEX 8532 generates
interrupts for Hot Plug events, and device-specific internal errors, and forwards interrupts received from
downstream ports. Both forwarded and internally generated interrupts are remapped and collapsed at the
upstream port.
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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