February, 2007
High-Priority Packets
8.5.3
High-Priority Packets
The previous sections discussed methods for optimizing latency in a single VC system. However,
a better solution for some traffic scenarios that require consistently low latency is to use a different VC.
The PEX 8532 does not support isochronous traffic that requires high-priority packets by way of
a switch with a time limit. However, it does provide a high-priority packet path throughout the entire
switch if there are two VCs and VC1 is configured with higher priority compared to VC0 in both the
ingress and egress ports.
VC1 includes independent credit, storage, and scheduling with respect to VC0. However, it shares the
wires in and out of the switch. At any point where there can be congestion between the two VCs, VC1 is
treated separately and preferentially to VC0. This occurs at the Ingress queues, internal fabric, and
Egress queues. For contention, VC1 packets are given priority over VC0 packets.
In this case, VC0 is earmarked for slower, bulk data transfer, and VC1 processes packets with a much
shorter latency if there is no over-subscription.
Two conditions are required to make the high-priority path meaningful:
• TC/VC mapping is symmetric across all ports
• All ports configure the Low-Priority Extended VC Count as 0, in the egress
Port VC Capability 1 register (offset 14Ch; default) to give VC1 the higher priority
• Certain TCs map to VC1 [VC0 Resource Control or VC1 Resource Control registers
(offsets 15Ch and 168h, respectively)] and the high-priority TLPs use the TCs that map to VC1
• VC1 is enabled on ingress and egress ports
8.5.4
8.5.5
Smaller Size Packets
The PEX 8532 uses a store-and-forward architecture. Without cut through, a packet must be completely
written into the PEX 8532’s internal packet RAM before the first byte of the packet can be transmitted
out of the egress port. Fall-through latency is a function of the packet size; therefore, the smaller the
packet size, the shorter the fall-through latency. The bulk of the latency is dictated by the amount of time
it takes for the packet to arrive. Narrower ingress ports contain correspondingly higher latency than
wider egress ports.
Power Management
Saving power and optimizing latency are typically two conflicting tasks. After a chip enters Power
Saving mode, the wakeup time when new Burst packets arrive always contributes to latency. For
latency-sensitive applications, it is recommended to use software to turn off the ASPM L0s entrance/
exit, as well as the L1 entrance/exit.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
115
PLX [ PLX TECHNOLOGY ]
