OXU200 Data Sheet
Oxford Semiconductor, Inc.
Table 8 OXU200
100-Pin LQFP
Pin Allocations (Sheet 1 of 2)
Pin
No.
Bits
16
Type
(1)
Name
Description
Processor Interface (33 pins)
2, 3, 4, 5, 8, 9, 10,
11, 13, 14, 15, 16,
96, 97, 98, 99
22, 23, 24, 25, 28,
29, 30 32, 33, 35
20
21
39
19
MSBCT
D
0
- D
15
16-bit data bus. Pull-up/pull-down can be controlled
through register 0x034, bits 2:1. Default is none
Address bus for direct address space of 2 Kbytes.
Default is pull-down
Write strobe. Pull-up can be disabled through register
0x034, bit 13. Default is pull-up
Read strobe. Pull-up can be disabled through register
0x034, bit 13. Default is pull-up
Chip select. Pull-up can be disabled through register
0x034, bit 13. Default is pull-up
Interrupt to the MCU.This pin can be software
configured as a driven output or open drain. Open
drain is the default
Hardware reset. Pull-up is always enabled
DMA request output
DMA acknowledge. Pull-up/pull-down can be
controlled through register 0x03A, bits 1:0. Default is
none
General purpose I/O
Digital/wide-range ground
Analog ground
1.8 V core power. V
REGOUT
must be used for the
supplies
Analog +3.3 V power
Digital +3.3 V power
Wide-range I/O +1.8 V to +3.3 V. If using +1.8 V,
V
REGOUT
may be used for these supplies
Data lines for USB peripheral port
Connect external reference resistor (12 KΩ +/- 1%) to
V
SSA
V
BUS
input used by the voltage comparators of the
peripheral port for connection
10
1
1
1
1
MSID
MSIU
MSIU
MSIU
MOCT
A
1
- A
10
/WR
/RD
/CS
/INT
86
89
90
1
1
1
MSIU
MOCT
MSI
/RESET
DRQ
ACK
General Purpose I/O (1 pin)
88
1, 12, 27, 41, 51,
65, 75, 83
42, 47, 69, 74, 82
6, 18, 40, 53, 57,
66, 84, 100
43, 48, 70, 73, 81
56, 78
7, 17, 26, 31, 85,
95
44, 45
46
72
1
8
5
8
5
2
6
BC
GPIO
V
SS
V
SSA
V
DD1.8
V
DD3.3A
V
DD3.3
V
DDW
Power & Ground (34 pins)
USB Interface (4 pins)
2
1
1
B
B
5I
D
P
, D
M
R
REF
V
BUS
8
External—Free Release
DS-0051 Mar 07
PLX [ PLX TECHNOLOGY ]
