Oxford Semiconductor, Inc.
OXU200 Data Sheet
Pin Layout
The OXU200 is supplied as a 100‐pin LQFP package and as a 64‐ball BGA
package. Figure 2 shows the pin layout of the 100‐pin OXU200‐LQAG
package.
Figure 2 OXU200 100-Pin LQFP Package (Top View)
V
DD 3.3A
V
DD 3.3A
XMODE
V
DD 1.8
V
DD 1.8
D
V
DD 3.3
V
DD1.8
V
SSA
V
BUS
V
SSA
NC
75
NC
NC
V
DD3.3
NC
V
REGOUT
V
DD3.3A
V
SSA
V
SS
V
DD1.8
V
DDW
/RESET
TEST
GPIO
DRQ
ACK
RSVD
0
NC
RSVD
2
RSVD
1
V
DDW
D
0
D
1
D
2
D
3
V
DD1.8
.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
74
73
72
71
70
69
68
67 66
65
64
63
62
61 60
59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
OSC
1
OSC
2
V
DD3.3A
V
SSA
R
REF
D
M
D
P
V
DD3.3A
V
SSA
V
SS
V
DD1.8
.
/CS
NC
NC
NC
A
10
NC
A
9
A
8
V
DDW
A
7
A
6
A
5
V
SS
V
DDW
NC
V
SS
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
V
SS
NC
NC
NC
NC
NC
NC
NC
OXU200-LQAG
2
3
4
5
6
7
8
9
10
11
NC
NC
12
13
14
15
16
17
18
19
20
21 22
23
24 25
D
11
V
DD1.8
/WR
A
1
V
DD1.8
V
SS
V
SS
V
DDW
/INT
/RD
D
12
D
6
D
7
D
8
D
10
D
14
A
2
A
3
NC
D
13
D
4
D
5
D
9
DS-0051
Mar 07
V
DDW
External—Free Release
D
15
A
4
7
PLX [ PLX TECHNOLOGY ]
