OXU200 Data Sheet
Oxford Semiconductor, Inc.
Table 9 OXU200 64-Ball BGA Ball Allocations (Sheet 2 of 2)
(1)
Pin
No.
Bits
Name
Description
Type
Clock Interface (2 pins)
G8
1
I
OSC
OSC
Input. A 12 MHz passive crystal should be connected across
the two pins (OSC and OSC ). Optionally, a 12 MHz oscillator
1
2
1
2
can be connected to OSC while keeping OSC unconnected
1
2
H8
1
O
Output
Internal Voltage Regulator (1 pin)
A8
1
O
V
Internal voltage regulator output of 1.8 V. This output must be
connected to the V supply of the chip (and may be
REGOUT
DD1.8
connected to V
if wide-range IO is at 1.8 V)
DDW
Test (2 pins)
B7
1
1
ID
I
TEST
Factory test mode. This pin should be grounded or left floating
(has an internal pull-down) for normal operation. Pull-down is
always enabled
D8
XMODE
This pin must be grounded for normal operation
Miscellaneous (7 pins)
B5, C5, B4
3
4
-
-
RSVD , RSVD , Reserved. These pins must be grounded
0
1
RSVD
2
A4, E8, F8, G4
NC
No connect. These pins should be left floating
Note to Table 9:
1
Type key: format is [(L)(W_)X(Y)(_Z(T))] where the following conventions apply:
L—Logic Level
W—Tolerance
X—Type
Input
Y—Pull
Pull up
Z—Drive
T—Tristate
Tristate
Normal
(2)
(3)
Multi-voltage:
3.3 V CMOS
2.5 V CMOS
1.8 V CMOS
5
5 V
I
U
D
T
M
C
3.3 V
O
Output
Pull down
S
Schmitt Trigger
B
Bidirectional
None
2
3
Program to 3.3, 2.5, or 1.8 V by setting the VIO voltage level.
Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14, mA, or 16 mA via the I/O Configuration
Register (0x034).
12
External—Free Release
DS-0051 Mar 07
PLX [ PLX TECHNOLOGY ]
