(Preliminary)PL611s-28
1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock
LAYOUT RECOMMENDATIONS
DFN-6L Evaluation Board
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this equals
ringing!
- Multiple VDD pins should be decoupled separately
for best performance.
- Long trace = Transmission Line. Without proper
termination this will cause reflections ( looks like
ringing ).
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Design long traces as “striplines” or “microstrips”
with defined impedance.
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1µF for
designs using crystals < 50MHz and 0.01µF for
designs using crystals > 50MHz.
- Match trace at one side to avoid reflections
bouncing back and forth.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20
To CMOS Input
50 line
Series Resistor
Use value to match output
buffer impedance to 50
trace. Typical value 30
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 6
PLL [ PHASELINK CORPORATION ]
