欢迎访问ic37.com |
会员登录 免费注册
发布采购

PL611S-28-XXXTIR 参数 Datasheet PDF下载

PL611S-28-XXXTIR图片预览
型号: PL611S-28-XXXTIR
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8V - 3.3V PicoPLLTM ,世界上最小的可编程时钟 [1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock]
分类和应用: 时钟
文件页数/大小: 9 页 / 324 K
品牌: PLL [ PHASELINK CORPORATION ]
 浏览型号PL611S-28-XXXTIR的Datasheet PDF文件第1页浏览型号PL611S-28-XXXTIR的Datasheet PDF文件第2页浏览型号PL611S-28-XXXTIR的Datasheet PDF文件第4页浏览型号PL611S-28-XXXTIR的Datasheet PDF文件第5页浏览型号PL611S-28-XXXTIR的Datasheet PDF文件第6页浏览型号PL611S-28-XXXTIR的Datasheet PDF文件第7页浏览型号PL611S-28-XXXTIR的Datasheet PDF文件第8页浏览型号PL611S-28-XXXTIR的Datasheet PDF文件第9页  
(Preliminary)PL611s-28  
1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock  
FUNCTIONAL DESCRIPTION  
PL611s-28 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-  
power, small form-factor applications. The PL611s-28 accepts a fundamental input crystal of 10MHz to 50MHz or  
reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 125MHz. This flexible  
design allows the PL611s-28 to deliver any PLL generated frequency, FREF (Crystal or Ref Clk) frequency or FREF  
/(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-28 are mentioned below:  
PLL Programming  
Output Enable (OE)  
The PLL in the PL611s-28 is fully programmable.  
The PLL is equipped with an 8-bit input frequency  
divider (R-Counter), and an 11-bit VCO frequency  
feedback loop divider (M-Counter). The output of  
the PLL is transferred to a 5-bit post VCO divider (P-  
Counter). The output frequency is determined by  
the following formula [FOUT = FREF * M / (R * P) ].  
The Output Enable feature allows the user to enable  
and disable the clock output(s) by toggling the OE  
pin. The OE pin incorporates a 60kΩ pull up  
resistor giving a default condition of logic “1”.  
The OE feature can be programmed to allow the  
output to float (Hi Z), or to operate in the ‘Active low’  
mode.  
Clock Output (CLK0)  
Power-Down Control (PDB)  
CLK0 is the main clock output. The output of CLK0  
can be configured as the PLL output (FVCO/(2*P)),  
FREF (Crystal or Ref Clk Frequency) output, or  
FREF/(2*P) output.  
The Power Down (PDB) feature allows the user to  
put the PL611s-28 into “Sleep Mode”. When  
activated (logic ‘0’), PDB ‘Disables the PLL, the  
oscillator circuitry, counters, and all other active  
circuitry. In Power Down mode the IC consumes  
<10µA of power. The PDB pin incorporates a 60kΩ  
pull up resistor giving a default condition of logic “1”.  
Clock Output (CLK1)  
The CLK1 feature allows the PL611s-28 to have an  
additional clock output. This output can be  
programmed to one of the following:  
The PDB feature can be programmed to allow the  
output to float (Hi Z), or to operate in the ‘Active low’  
mode.  
FREF - Reference (Crystal or Ref Clk) Frequency  
FREF / 2  
CLK0  
Frequency Select (FSEL)  
CLK0 / 2  
The Frequency Select (FSEL) feature allows the  
PL611s-28 to switch between two pre-programmed  
outputs allowing the device “On the Fly” frequency  
switching. The FSEL pin incorporates a 60kΩ pull  
up resistor giving a default condition of logic “1”.  
The output drive level can be programmed to Low  
Drive (4mA), Standard Drive (8mA) or High Drive  
(16mA) for each clock independently. The maximum  
output frequency is 125MHz.  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 3