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PL611S-28-XXXTIR 参数 Datasheet PDF下载

PL611S-28-XXXTIR图片预览
型号: PL611S-28-XXXTIR
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8V - 3.3V PicoPLLTM ,世界上最小的可编程时钟 [1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock]
分类和应用: 时钟
文件页数/大小: 9 页 / 324 K
品牌: PLL [ PHASELINK CORPORATION ]
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(Preliminary)PL611s-28  
1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock  
ELECTRICAL SPECIFICATIONS  
ABSOLUTE MAXIMUM RATINGS  
PARAMETERS  
SYMBOL  
MIN.  
MAX.  
UNITS  
Supply Voltage Range  
VDD  
7
V
V
-0.5  
-0.5  
-0.5  
Input Voltage Range  
V
VDD+0.5  
VDD+0.5  
260  
I
Output Voltage Range  
V
V
O
Soldering Temperature (Green package)  
Data Retention @ 85°C  
°C  
Year  
°C  
°C  
10  
Storage Temperature  
-65  
-40  
150  
85  
T
S
Ambient Operating Temperature*  
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device  
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above  
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.  
AC SPECIFICATIONS  
PARAMETERS  
CONDITIONS  
MIN.  
TYP.  
MAX. UNITS  
Crystal Input Frequency (XIN)  
Fundamental Crystal  
10  
50  
MHz  
@ VDD =3.3V  
200  
166  
133  
VDD  
Input (FIN) Frequency  
MHz  
@ VDD =2.5V  
@ VDD =1.8V  
Input (FIN) Signal Amplitude  
Input (FIN) Signal Amplitude  
Internally AC coupled (High Frequency)  
0.9  
0.1  
Vpp  
Vpp  
Internally AC coupled (Low Frequency)  
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz  
VDD  
@ VDD =3.3V  
125  
90  
65  
2
MHz  
MHz  
MHz  
ms  
Output Frequency  
@ VDD =2.5V  
@ VDD =1.8V  
Settling Time  
At power-up (after VDD increases over 1.62V)  
OE Function; Ta=25º C, 15pF Load  
PDB Function; Ta=25º C, 15pF Load  
Frequency vs. VDD +/-10%  
10  
2
ns  
Output Enable Time  
ms  
VDD Sensitivity  
Output Rise Time  
Output Fall Time  
-2  
2
ppm  
ns  
15pF Load, 10/90% VDD, High Drive, 3.3V  
15pF Load, 90/10% VDD, High Drive, 3.3V  
1.2  
1.2  
50  
1.7  
1.7  
55  
ns  
Duty Cycle  
VDD /2  
45  
%
Period Jitter,Pk-to-Pk*  
(measured from 10,000 samples) GND.  
With capacitive decoupling between VDD and  
70  
ps  
* Note: Jitter performance depends on the programming parameters.  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 4