(Preliminary)PL611s-28
1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK[0:1]
Output Frequency
Programmable
Input/Output
Output Drive Strength
FOUT = FREF * M / (R * P)
Three optional drive strengths to
choose from:
One output pin can be configured
as:
Where M = 11 bit
R = 8 bit
P = 5 bit
• Low: 4mA
• OE - input
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
• Std: 8mA (default)
• High: 16mA
• PDB - input
• FSEL – input
• HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Pin Assignment
SOT SC70 DFN
Pin # Pin# Pin#
Name
Type
Description
This programmable I/O pin can be configured as an Output Enable
(OE) input, Power Down (PDB) input, On-the-Fly Frequency Switching
Selector (FSEL)input or CLK1 clock output. This pin has an internal
60KΩ pull up resistor (OE, PDB & FSEL Only).
The OE and PDB features can be programmed to allow the output to
float (Hi Z), or to operate in the ‘Active low’ mode.
OE, PDB,
FSEL, CLK1
1
2
2
I/O
State
OE
PDB
FSEL
0
Disable CLK
Normal mode
Power Down Mode
Normal mode
Frequency ‘2’
Frequency ‘1’
1 (default)
GND
2
3
1
3
3
1
P
I
GND connection
XIN, FIN
Crystal or Reference input pin
Crystal Output pin
XOUT
4
4
6
O
Do Not Connect (DNC ) when FIN is present
VDD connection
VDD
5
6
5
6
5
4
P
CLK0
O
Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 2
PLL [ PHASELINK CORPORATION ]
