PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
2. AC Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
PLL500-27
MIN.
TYP.
MAX.
UNITS
27
65
65
Input Crystal Frequency
MHz
PLL500-37
130
200
PLL500-47
100
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V
1.15
3.7
ns
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
45
50
55
%
mA
±50
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
ms
From power valid
10
TVCXOSTB
300
ppm
XTAL C0/C1 < 250
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
ppm
ppm/V
%
0V ≤ VCON ≤ 3.3V
±150
100
5
Frequency change with
VDD varied +/- 10%
Power Supply Rejection
PWSRR
-1
+1
ppm
2000
45
VCON pin input impedance
VCON modulation BW
kΩ
kHz
0V ≤ VCON ≤ 3.3V, -3dB
Note: Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not
production tested to any specific limits.
4. Jitter and Phase Noise specification
PARAMETERS
RMS Period Jitter
CONDITIONS
MIN.
TYP.
MAX.
UNITS
With capacitive decoupling
between VDD and GND.
2.5
ps
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
-80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-110
-130
-138
-145
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 3
PLL [ PHASELINK CORPORATION ]
