PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
FEATURES
PIN CONFIGURATION
•
VCXO output for the 27MHz to 200MHz range
-
-
-
PLL500-27: 27MHz to 65MHz
PLL500-37: 65MHz to 130MHz
PLL500-47: 100MHz to 200MHz
XIN
OE^
VIN
XOUT
DS^
1
2
3
4
8
7
6
5
VDD*
CLK
•
•
•
Low phase noise (-130 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable output drive (Standard or High drive).
GND
-
-
Standard: 12mA drive capability at TTL level.
High: 36mA drive capability at TTL level.
^: Denotes internal Pull-up
•
•
•
•
•
•
Fundamental crystal input.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5-3.3V operation.
DIE PAD LAYOUT
8
1
Die ID:
Available in 8-Pin SOIC or DIE.
7
6
PLL500-27B:
2
C500A0505-05P
DESCRIPTION
PLL500-37BDC:
C500A0505-05Q
3
4
The PLL500-27/-37/-47 are a low cost, high perform-
ance, low phase noise, and high linearity VCXO fam-
ily for the 27 to 200MHz range, providing less than -
130dBc at 10kHz offset. The very low jitter (2.5 ps
RMS period jitter) makes these chips ideal for appli-
cations requiring voltage controlled frequency
sources. The IC’s are designed to accept fundamen-
tal resonant mode crystals.
5
PLL500-47BDC:
C500A0505-05R
FREQUENCY RANGE
PART #
MULTIPLIER
No PLL
FREQUENCY
27 – 65 MHz
PLL500-27B
PLL500-37B
PLL500-47B
No PLL
65 – 130 MHz
100 – 200 MHz
No PLL
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 1
PLL [ PHASELINK CORPORATION ]
