PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
PIN AND PAD DESCRIPTION
Die Pad Position
Name
Pin#
Type
Description
X (µm)
Y (µm)
XIN
OE
1
2
94.183
768.599
I
I
Crystal input pin.
Output Enable input pin. Disables the output when low. Internal
pull-up enables output by default if pin is not connected low.
94.157
605.029
VCON
GND
CLK
3
4
5
6
94.183
94.193
331.756
140.379
203.866
455.726
I
Frequency control voltage input pin.
Ground pin.
P
O
P
715.472
715.307
Output clock pin.
VDD
VDD power supply pin.
Output drive select pin. High drive if set to ‘0’. Low drive if set
to ‘1’. Internal pull-up.
DRIVSEL
XOUT
7
8
715.472
476.906
626.716
888.881
I
I
Crystal output pin. Ref clock input.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
Input Voltage Range
4.6
V
V
VCC
VI
-0.5
-0.5
-0.5
VCC+0.5
VCC+0.5
240
Output Voltage Range
Soldering Temperature
Storage Temperature
V
VO
°C
°C
°C
-65
-40
150
TS
Ambient Operating Temperature
+85
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 2
PLL [ PHASELINK CORPORATION ]
