Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IEC 60958 inputs
Vi(p-p)
input voltage (peak-to-peak
value)
0.2
0.5
3.3
V
Ri
input resistance
−
−
−
6
−
−
−
kΩ
mV
−
Vhys
IDD(diff)
hysteresis voltage
40
tbf
IDD(DAC,input)/IDD(DAC,no input)
Power consumption
Ptot
total power consumption
IEC 60958 input; fs = 48 kHz
DAC in playback mode
−
74
63
−
−
mW
mW
DAC in Power-down mode −
Notes
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit.
2. When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100 Ω must be used in
order to prevent oscillations in the output.
16 TIMING CHARACTERISTICS
VDD = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; unless otherwise specified.
SYMBOL
Device reset
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
trst
reset time
−
250
−
µs
PLL lock time
tlock
time-to-lock
fs = 32 kHz
−
−
−
−
85.0
63.0
60.0
40.0
−
−
−
−
ms
ms
ms
ms
fs = 44.1 kHz
fs = 48 kHz
fs = 96 kHz
I2S-bus interface (see Fig.20)
Tcy(BCK) bit clock period
tBCKH
1
/
−
−
−
−
−
−
−
−
−
ms
ns
ns
ns
ns
ns
ns
ns
128fs
bit clock HIGH time
bit clock LOW time
rise time
30
30
−
−
tBCKL
−
tr
20
20
−
tf
fall time
−
tsu(DATAI)
th(DATAI)
td(DATAO-BCK)
data input set-up time
data input hold time
10
10
−
−
data output to bit clock
delay
30
td(DATAO-WS)
data output to word
select delay
−
−
30
ns
th(DATAO)
tsu(WS)
th(WS)
data output hold time
word select set-up time
word select hold time
0
−
−
−
−
−
−
ns
ns
ns
10
10
2003 Apr 10
66
NXP [ NXP ]
