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UDA1355H 参数 Datasheet PDF下载

UDA1355H图片预览
型号: UDA1355H
PDF下载: 下载PDF文件 查看货源
内容描述: 有SPDIF接口,立体声音频编解码器 [Stereo audio codec with SPDIF interface]
分类和应用: 解码器编解码器消费电路商用集成电路光电二极管
文件页数/大小: 76 页 / 311 K
品牌: NXP [ NXP ]
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Philips Semiconductors  
Preliminary specification  
Stereo audio codec with SPDIF interface  
UDA1355H  
Programmable digital silence detector  
which can generate level II output signals with CMOS  
levels. In microcontroller mode the UDA1355H offers a  
large variety of possibilities for defining signal flows  
through the IC, offering a flexible analog, digital and SPDIF  
converter chip with possibilities for off-chip sound  
processing via the digital input and output interface.  
Interpolating filter (fs to 64fs or fs to 128fs) comprising a  
recursive and a FIR filter in cascade  
Selectable fifth-order noise shaper operating at 64fs or  
third-order noise shaper operating at 128fs (specially for  
low sampling frequencies, e.g. 16 kHz) generating  
bitstream for DAC  
A lock indicator is available on pin LOCK when the  
IEC 60958 decoder and the clock regeneration  
mechanism is in lock. By default the DAC output and the  
digital data interface output are muted when the decoder  
is not in lock.  
Filter Stream DAC (FSDAC)  
In microcontroller mode:  
– Left and right volume control (for balance control)  
0 to 78 dB and −∞  
The UDA1355H contains two clock systems which can run  
at independent frequencies, allowing to lock-on to an  
incoming SPDIF or digital audio signal, and in the mean  
time generating a stable signal by means of the crystal  
oscillator for driving, for example, the ADC or SPDIF  
output signal.  
– Left and right bass boost and treble control  
– Optional resonant bass boost control  
– Mixing possibility of two data streams.  
2
GENERAL DESCRIPTION  
Using the crystal oscillator (which requires a 12.288 MHz  
crystal) and the on-chip low jitter PLL, all standard audio  
sampling frequencies (fs = 32, 44.1 and 48 kHz including  
half and double these frequencies) can be generated.  
The UDA1355H is a single-chip IEC 60958 decoder and  
encoder with integrated stereo digital-to-analog converters  
and analog-to-digital converters employing bitstream  
conversion techniques.  
The UDA1355H has a selectable one-of-four SPDIF input  
(accepting level I, II and III timing) and one SPDIF output  
3
ORDERING INFORMATION  
TYPE  
PACKAGE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
UDA1355H  
QFP44  
plastic quad flat package; 44 leads (lead length 1.3 mm); body  
SOT307-2  
10 × 10 × 1.75 mm  
2003 Apr 10  
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