Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
1
FEATURES
General
1.1
• 2.7 to 3.6 V power supply
• Integrated digital interpolator filter and Digital-to-Analog
Converter (DAC)
• 24-bit data path in interpolator
• No analog post filtering required for DAC
• 32, 44.1 and 48 kHz output frequencies (including
double and half of these frequencies) supported in
microcontroller mode
• Integrated Analog-to-Digital Converter (ADC),
Programmable Gain Amplifier (PGA) and digital
decimator filter
• Via microcontroller, 40 status bits can be set for left and
right channel.
• 24-bit data path in decimator
• Master or slave mode for digital audio data I/O interface
• I2S-bus, MSB-justified, LSB-justified 16, 18, 20,
1.5
Digital I/O interface
and 24 bits formats supported on digital I/O interface.
• Supports sampling frequencies from 16 to 100 kHz
• Supported static mode:
1.2
Control
– I2S-bus format
• Controlled by means of static pins or microcontroller
(L3-bus or I2C-bus) interface.
– LSB-justified 16 and 24 bits format
– MSB-justified format.
1.3
IEC 60958 input
• Supported microcontroller mode:
– I2S-bus format
• On-chip amplifier for converting IEC 60958 input to
CMOS levels
– LSB-justified 16, 18, 20 or 24 bits format
– MSB-justified format.
• Supports level I, II and III timing
• Selectable IEC 60958 input channel, one of four
• Supports input frequencies from 28 to 96 kHz
• Lock indication signal available on pin LOCK
• BCK and WS signals can be slave or master, depending
on application mode.
1.6
ADC digital sound processing
• 40 status bits can be read for left and right channel via
L3-bus or I2C-bus
• Supports sampling frequencies from 16 to 100 kHz
• Channel status bits available via L3-bus or I2C-bus: lock,
pre-emphasis, audio sample frequency, two channel
Pulse Code Modulation (PCM) indication and clock
accuracy
• Analog front-end includes a 0 to +24 dB PGA in steps of
3 dB, selectable via microcontroller interface
• Digital independent left and right volume control of
+24 to −63.5 dB in steps of 0.5 dB via microcontroller
interface
• Pre-emphasis information of incoming IEC 60958
bitstream available in register
• Bitstream ADC operating at 64fs
• Detection of digital data preamble, such as AC3,
available on pin in microcontroller mode.
• Comb filter decreases sample rate from 64fs to 8fs
• Decimator filter (8fs to fs) made of a cascade of three
FIR half-band filters.
1.4
IEC 60958 output
• CMOS output level converted to IEC 60958 output
signal
1.7
DAC digital sound processing
• Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio
sampling frequencies
• Full-swing digital signal, with level II timing using crystal
oscillator clock
• Automatic de-emphasis when using IEC 60958 to DAC
• 32, 44.1 and 48 kHz output frequencies supported in
• Soft mute made of a cosine roll-off circuit selectable via
static mode
pin MUTE or L3-bus interface
2003 Apr 10
3
NXP [ NXP ]
