Philips Semiconductors
Product specification
High speed CAN transceiver
TJA1041A
The tdom(TXD) timer defines the minimum possible bit rate
of 40 kbit/s. The transmitter remains disabled until the
local failure flag is cleared.
junction temperature exceeds the shutdown junction
temperature Tj(sd). The transmitter remains disabled until
the local failure flag is cleared.
RXD RECESSIVE CLAMPING DETECTION
Recessive bus voltage stabilization
An RXD pin clamped to HIGH level will prevent the
controller connected to this pin from recognizing a bus
dominant state. So the controller can start messages at
any time, which is likely to disturb all bus communication.
RXD recessive clamping detection prevents this effect by
disabling the transmitter when the bus is in dominant state
without RXD reflecting this. The transmitter remains
disabled until the local failure flag is cleared.
In recessive state the output impedance of transceivers is
relatively high. In a partially powered network (supply
voltage is off in some of the nodes) any deactivated
transceiver with a significant leakage current is likely to
load the recessive bus to ground. This will cause a
common-mode voltage step each time transmission starts,
resulting in increased ElectroMagnetic Emission (EME).
Using pin SPLIT of the TJA1041A in combination with split
termination (see Fig.5) will reduce this step effect. In
normal mode and pwon/listen-only mode pin SPLIT
provides a stabilized 0.5VCC DC voltage. In standby mode,
go-to-sleep command mode and sleep mode pin SPLIT is
set floating.
TXD-TO-RXD SHORT-CIRCUIT DETECTION
A short-circuit between pins RXD and TXD would keep the
bus in a permanent dominant state once the bus is driven
dominant, because the low-side driver of RXD is typically
stronger than the high-side driver of the controller
connected to TXD. The TXD-to-RXD short-circuit
detection prevents such a network lock-up by disabling the
transmitter. The transmitter remains disabled until the local
failure flag is cleared.
I/O level adapter
The TJA1041A is equipped with a built-in I/O-level
adapter. By using the supply voltage of the controller (to be
supplied at pin VI/O) the level adapter ratio-metrically
scales the I/O-levels of the transceiver. For pins TXD, STB
and EN the digital input threshold level is adjusted, and for
pins RXD and ERR the HIGH-level output voltage is
adjusted. This allows the transceiver to be directly
interfaced with controllers on supply voltages between
2.8 V and 5.25 V, without the need for glue logic.
BUS DOMINANT CLAMPING DETECTION
A CAN bus short circuit (to VBAT, VCC or GND) or a failure
in one of the other network nodes could result in a
differential voltage on the bus high enough to represent a
bus dominant state. Because a node will not start
transmission if the bus is dominant, the normal bus failure
detection will not detect this failure, but the bus dominant
clamping detection will. The local failure flag is set if the
Pin WAKE
Pin WAKE of the TJA1041A allows local wake-up
triggering by a LOW to HIGH state change as well as a
HIGH to LOW state change. This gives maximum flexibility
when designing a local wake-up circuit. To keep current
consumption at a minimum, after a twake delay the internal
bias voltage of pin WAKE will follow the logic state of this
pin. A HIGH level on pin WAKE is followed by an internal
pull-up to VBAT. A LOW level on pin WAKE is followed by
an internal pull-down towards GND. To ensure EMI
performance in applications not using local wake-up it is
recommended to connect pin WAKE to pin VBAT or to pin
GND.
dominant state on the bus persists for longer than tdom(bus)
By checking this flag, the controller can determine if a
.
clamped bus is blocking network communication. There is
no need to disable the transmitter. Note that the local
failure flag does not retain a bus dominant clamping
failure, and is released as soon as the bus returns to
recessive state.
OVER-TEMPERATURE DETECTION
To protect the output drivers of the transceiver against
overheating, the transmitter will be disabled if the virtual
2004 Feb 20
10
NXP [ NXP ]
