欢迎访问ic37.com |
会员登录 免费注册
发布采购

TDA4856 参数 Datasheet PDF下载

TDA4856图片预览
型号: TDA4856
PDF下载: 下载PDF文件 查看货源
内容描述: I2C总线自动同步偏转控制器的PC显示器 [I2C-bus autosync deflection controller for PC monitors]
分类和应用: 显示器控制器PC
文件页数/大小: 56 页 / 983 K
品牌: NXP [ NXP ]
 浏览型号TDA4856的Datasheet PDF文件第33页浏览型号TDA4856的Datasheet PDF文件第34页浏览型号TDA4856的Datasheet PDF文件第35页浏览型号TDA4856的Datasheet PDF文件第36页浏览型号TDA4856的Datasheet PDF文件第38页浏览型号TDA4856的Datasheet PDF文件第39页浏览型号TDA4856的Datasheet PDF文件第40页浏览型号TDA4856的Datasheet PDF文件第41页  
Philips Semiconductors  
Product specification  
I2C-bus autosync deflection controller for  
PC monitors  
TDA4856  
Start-up procedure  
VCC < 8.3 V:  
START  
As long as the supply voltage is too low for correct  
operation, the IC will give no acknowledge due to  
internal Power-on reset (POR)  
Power-down mode (XXXX XXXX)  
L1  
L2  
no acknowledge is given by IC  
all register contents are random  
Supply current is 9 mA or less.  
V
> 8.3 V  
VCC > 8.3 V:  
CC  
The internal POR has ended and the IC is in standby  
Standby mode (XXXX XX01)  
mode  
STDBY = 1  
SOFTST = 0  
Control bits STDBY and SOFTST are reset to their start  
all other register contents are random  
values  
All other register contents are random  
Pin HUNLOCK is at HIGH-level.  
Setting control bit STDBY = 0:  
S
8CH  
A
1AH  
A
00H  
A P  
Protection mode (XXXX XX00)  
Enables internal power supply  
STDBY = 0  
SOFTST = 0  
all other register contents are random  
Supply current increases from 9 to 70 mA  
When VCC < 8.6 V register SOFTST cannot be set by  
the I2C-bus  
S
8CH  
A
SAD  
A
DATA A P  
Output stages are disabled, except the vertical output  
Pin HUNLOCK is at HIGH-level.  
Protection mode (XXXX XX00)  
Setting all registers to defined values:  
STDBY = 0  
SOFTST = 0  
Due to the hardware configuration of the IC  
(no auto-increment) any register setting needs a  
complete 3-byte I2C-bus data transfer as follows:  
START - IC address - subaddress - data - STOP.  
registers are pre-set  
no  
all registers defined?  
yes  
Setting control bit SOFTST = 1:  
L3  
S
8CH  
A
1AH  
A
02H  
A P  
Before starting the soft-start sequence a delay of  
minimum 80 ms is necessary to obtain correct function  
of the horizontal drive  
Soft-start sequence (XXXX XX10)  
HDRV duty cycle increases  
BDRV duty cycle increases  
PLL1 and PLL2 are enabled.  
STDBY = 0  
SOFTST = 1  
Operating mode (XXXX XX10)  
IC in full operation:  
STDBY = 0  
SOFTST = 1  
Pin HUNLOCK is at LOW-level when PLL1 is locked  
Any change of the register content will result in  
immediate change of the output behaviour  
no  
no  
change/refresh of data?  
yes  
SOFTST = 0?  
yes  
Setting control bit SOFTST = 0 is the only way (except  
power-down via pin VCC) to leave the operating mode.  
(1)  
L4  
S
8CH  
A
SAD  
A
DATA A P  
Soft-down sequence:  
MGL791  
See L4 of Fig.19 for starting the soft-down sequence.  
(1) See Fig.19.  
Fig.18 I2C-bus flow for start-up.  
1999 Jul 13  
37  
 复制成功!