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TDA4856 参数 Datasheet PDF下载

TDA4856图片预览
型号: TDA4856
PDF下载: 下载PDF文件 查看货源
内容描述: I2C总线自动同步偏转控制器的PC显示器 [I2C-bus autosync deflection controller for PC monitors]
分类和应用: 显示器控制器PC
文件页数/大小: 56 页 / 983 K
品牌: NXP [ NXP ]
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Philips Semiconductors  
Product specification  
I2C-bus autosync deflection controller for  
PC monitors  
TDA4856  
Table 3 Activation of protection mode  
Power dip recognition  
In standby mode the I2C-bus will only answer with an  
acknowledge, when data is sent to control register with  
subaddress 1AH. This register contains the standby and  
soft start control bit.  
ACTIVATION  
RESET  
Low supply voltage at pin 10 increase supply voltage;  
reload registers;  
soft start via I2C-bus  
If the I2C-bus master transmits data to another register, an  
aknowledge is given after the chip address and the  
subaddress; an acknowledge is not given after the data.  
This indicates that only in soft start mode data can be  
stored into normal registers.  
Power dip, below 8.1 V  
reload registers;  
soft start via I2C-bus or  
via supply voltage  
X-ray protection XRAY  
(pin 2) triggered  
reload registers;  
soft start via I2C-bus  
If the supply voltage dips under 8.1 V the TDA4856 leaves  
normal operation mode and changes into standby mode.  
The microcontroller can check this state by sending data  
into a register with the subaddress 0XH. The acknowledge  
will only be given on the data if the TDA4856 is active.  
HPLL2 (pin 30) externally  
pulled to ground  
release pin 30  
When the protection mode is active, several pins of the  
TDA4856 are forced into a defined state:  
Due to this behaviour the start-up of the TDA4856 is  
defined as follows. The first data that is transferred to the  
TDA4856 must be sent to the control register with  
subaddress 1AH. Any other subaddress will not lead to an  
acknowledge. This is a limitation in checking the  
I2C-busses of the monitor during start-up.  
HDRV (horizontal driver output) is floating  
BDRV (B+ control driver output) is floating  
HUNLOCK (indicates, that the frequency-to-voltage  
converter is out of lock) is floating (HIGH-level via  
external pull-up resistor)  
CLBL provides a continuous blanking signal  
The capacitor at HPLL2 is discharged.  
If the soft start procedure is activated via the I2C-bus, all of  
these actions will be performed in a well defined sequence  
(see Figs 24 and 25).  
1999 Jul 13  
13  
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