Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4841PS
Pulse diagrams
4.0 V
handbook, full pagewidth
automatic trigger level
3.8 V synchronized trigger level
vertical oscillator sawtooth
at VCAP (pin 24)
1.4 V
vertical sync pulse
inhibited
internal trigger
inhibit window
(typical 4 ms)
vertical blanking pulse
at CLBL (pin 16)
vertical blanking pulse
at HUNLOCK (pin 17)
I
VOUT1
differential output currents
VOUT1 (pin 13) and
VOUT2 (pin 12)
I
VOUT2
7.0 V maximum
EW drive waveform
at EWDRV (pin 11)
DC shift 3.6 V maximum
low-level 1.2 V fixed
MGM075
Fig.14 Pulse diagram for vertical part.
31
1999 Oct 25
NXP [ NXP ]
