Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
HS
handbook, full pagewidth
PXQ (only in direct mode)
ACTIVE VIDEO WINDOW
BXO
(NumBytes/2) × scale ratio
SCALING
result
WINDOW
field/
frame
MGG265
line
Fig.26 Reference signals for scaling window for direct and line memory mode.
7.10.2.2 Direct mode
7.10.2.3 Line memory mode
The timing reference signals (VS, HS, LLC and FID) are
taken from port A or port B. The BRS has to deliver pixel
with pixel clock of 1⁄2LLC to the D1 port. To ensure that
there are no dropouts, a simple underflow handling is
performed by the DMA read module. If the PCI load is big
and a FIFO underflow occurs, the DMA read module uses
a grey value (10H for luminance, 80H for chrominance) or
the last pixel as a substitute. The FIFO control counts the
failed requests and removes the late values from the FIFO
hoping to catch up for lost time to the end of a line. At the
end of a line given by the external source the DMA tries to
read the data of the new line. This time is defined by the
horizontal offset (BXO) of the input acquisition, see Fig.26.
The timing reference signals (VS, HS, LLC and FID) are
taken from port A or port B. The access time could be
extended by using a line memory at the D1 interface. If a
FIFO underflow occurs during the active processing, the
DMA read unit waits for the next valid data hoping to catch
up for the lost time during the horizontal blanking interval.
The timing is retriggered by the H-sync and V-sync.
Therefore it is possible, depending on the PCI load, that a
line or a part of a line is read multiple from the line memory.
The PXQ is used as a write enable signal (see Fig.27).
The PXQ can be used as KEY signal for the On Screen
Display (OSD) data to support panning, if the video
window has no full screen format.
1998 Apr 09
79
NXP [ NXP ]
