Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.11.2 BINARY RATIO SCALER OUTPUT FORMATS
All YUV formats are based on CCIR coding:
Luminance Y in straight binary:
Black: Y = 16 of 256 linear coding
White: Y = 235 of 256 linear coding.
Colour difference signals UV in offset binary:
No colour: U = V = 128 of 256 steps
Full colour: U = V = 128 ±112 steps.
The following formats use video FIFO 3, DMA Channel 3 and are packed formats.
• YUV 4 : 2 : 2 U and V sampled co-sided with first Y sample (of 2 samples in-line). Byte phase of the first sample each
line is defined by bit 0 and bit 1 of DMA base address.
Table 65 YUV 4 : 2 : 2 formats
PACKING WITHIN 32-BIT Dword
BIT 31 TO BIT 24
BIT 23 TO BIT 16
BIT 15 TO BIT 8
BIT 7 TO BIT 0
Y1
V0
Y0
U0
7.11.2.1 VBI data formats
• Y8; uses only the Y portion of the data stream and packs four bytes in one Dword
• YUV 4 : 2 : 2; packs two pixel into one Dword, the order is Y1, V0, Y0, U0
• 1-bit format; the Y1 format is a 1-bit format which packs 32 times the most significant bit of luminance (Y) into one
Dword, the first bit is bit 31 of the Dword
• 2-bit format; the Y2 format is a 2-bit format which packs 16 times the two most significant bits of luminance (Y) into
one Dword, the first bit is bit 31 of the Dword.
7.12 Scaler register
7.12.1 INITIAL SETTING OF DUAL D1 INTERFACE
The initial settings of the Dual D1 interface contains all control bits of the scaler part which do not change during a cyclic
processing of the video path. These control bits must be initialized at the beginning of the processing. The different
upload conditions of the video path depend on these control bits. Changing these bits during the active processing can
cause a valid UPLOAD.
1998 Apr 09
83
NXP [ NXP ]
