Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
The PCI source data is defined by the base address
(BaseOdd3 and BaseEven3), the distance between the
start addresses of two consecutive lines of a field (Pitch3),
the number of lines per field of the source frame
(NumLines3) and the number of bytes per line of the
source frame (NumByte3). The programmer must provide
correct scaling settings to fulfil the target window
requirements. The pitch has to be Dword aligned.
7.10.2.1 Field memory mode
In the field memory mode the SAA7146A takes a vertical
sync signal as a timing reference signal. A reset signal for
a field memory and a PXQ as write enable are generated
within the circuit and both are sent to port A or port B.
In this mode the pixel clock depends on the PCI load.
The pixels are provided to the DD1 port with maximum
1⁄2LLC (CCIR 656), the picture rate is restricted by the
vertical timing reference. Since the transfer works without
losing any data the pixel clock can be varied, therefore an
external field memory is needed at the DD1 interface.
The SAA7146A writes its data continuously to this
memory. The video window size depends on the selected
window size in the system memory, the frame buffer
(Numlines, Numbytes, pitch and base address) and the
selected scaling ratio.
7.10.2 PLAYBACK MODE
The SAA7146A offers three different modes to support the
playback mode for various systems. The Binary Ratio
Scaler (BRS) inputs data from FIFO 3, therefore the DMA3
is in master read operation. The scaling result is passed to
the DD1 output.
The following sections describe the three different modes:
field memory mode, direct mode and line memory mode.
LLC
VS DATA
D1 INTERFACE
BRS
field
reset
PXQ
(write enable)
handbook, full pagewidth
PXQ
DATA
FIFO empty
DATA
DMA
READ
Dword request
FIFO3
PCI
MGG266
Fig.25 Sync and data path for field memory mode.
1998 Apr 09
78
NXP [ NXP ]
