Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
VERTICAL
SCALE
RATIO
BCS
(CONTR. | SAT.)
= X/Y × 64
COEFFICIENT
SEQUENCE (EXAMPLE)
WEIGHT
SUM
YACL
CYA; CYB
DCGY
1
1
16
⁄
⁄
17 to 1⁄18
(964)
16
1111 1111 1 1 1111 1111
2212 2212 2 2 2122 2122
1222 2222 1 1 2222 2221
...
FF, 00
44, BB
01, FE
...
18
32
32
...
3
4
18
1
1
4
...
...
...
4
...
1
⁄
23 to 1⁄24
22
1111 2222 1111
1111 2222 1111
0F, F0
32
(980)
1121 1212 1121
1211 2121 1211
AD, 52
32
4
1
The vertical start phase offset is defined by
7.9.2.6
LPI mode (scaling factor range 1 to 1⁄2; register
YP
⁄
64 (YP = 0 to 64):
bit YACM = 0)
• YP = 0: offset = 0 geometrical position of 1st
lineout = 1st linein
• YP = 64: offset = 64
⁄64 = 1 geometrical position of
1st lineout = 2nd linein.
To preserve the signal quality for slight vertical
downscales (scaling factors 1 to 1⁄2) Linear Phase
Interpolation (LPI) between consecutive lines is
implemented to generate geometrically correct vertical
output lines. Thus, the new geometric position between
lines N and N + 1 can be calculated.
Finally 3 special modes are to be emphasized:
1. Bypass (YSCI = 0, YP = 64); each lineout is equivalent
A new output line is calculated by weighting the samples
‘p’ of lines N and N + 1 with the normalized distance to the
newly calculated position:
to corresponding linein
2. Low-pass (YSCI = 0, YP < 64); e.g. YP = 32: average
value of 2 lines (1 + z−h filter)
3. For processing of interlaced input signals the LPI
mode must be used (ACCU mode would cause ‘line
pairing’ problems). The scaling start phase for odd and
even field have to be set to:
handbook, halfpage
YPeven = 3⁄2 × YPodd (line 1 = odd)
input lines
N
I
Distance = 1 N + 1
I
In modes 1 and 2 the first input line is fed to the output
(without processing), so that the number of output lines
equals the number of input lines
I
M
I
new calculated position line
of output line M
A
(1 − A)
MHB107
7.9.2.7
Flip option (Mirror = 1)
Fig.22 Calculation of output lines.
For both vertical scaling modes there is a flip option
‘mirroring’ available for input lines with a maximum of
384 pixels. In the case of full screen pictures (e.g.
768 × 576) that have to be flipped, they first have to be
downscaled to 384 pixel/line in the horizontal prescaling
unit and after vertical processing (flipping) they may be
rezoomed to the original 768 pixels/line in the following
VPD.
p(M) = A × p(N + 1) + (1 − A) × p(N); where A = 0 to 63⁄64.
With NOL = Number of Output Lines and NIL = Number of
Input Lines the scaler register bits YSCI (scaling
increment) and YP (scaling start phase) have to be set
according to the following equations:
It should be noted that, when using the flip option, the last
input line can not be displayed at the output.
• YSCI = INT [1024 × (NIL/(NOL − 1)] scaling increment
• YPx = INT [YSCI⁄16] scaling start phase (recommended
value).
1998 Apr 09
75
NXP [ NXP ]
